As the resolutions of displays such as a TV or a monitor increase, a larger amount of data needs to be transmitted. Therefore, when data is transmitted at a high data rate, the most Electromagnetic Interference (EMI) or Radio Frequency Interference (RFI) occurs in a data transmission line between a timing controller and a source driver, which is a column driving integration circuit. To reduce the interference, a small signal differential transmission scheme may be used, such as Reduced Swing Differential Signaling (RSDS) or mini-Low Voltage Differential Signaling (mini-LVDS).
Along with an increase in data rate, RSDS and mini-LVDS suffer from degradation of signal quality because a plurality of source drivers share a data line and a clock line. Impedance mismatch occurs at points where the lines are branched to the source drivers. In this context, Point-to-Point Differential Signaling (PPDS) has recently been proposed overseas, in which a timing controller is connected to a source driver in a one-to-one correspondence. Korea has also developed such a scheme.
Although for data, a timing controller is connected to source drivers in a one-to-one correspondence, a plurality of source drivers share a clock signal in PPDS. As a result, PPDS increases the timing skew error between the clock signal and the data signal during high-speed data transmission, thereby making it difficult to increase a transmission rate.
Meanwhile, the scheme developed in Korea transmits a clock signal and a data or control signal serially on one transmission line. Since the clock signal and the data signal are transmitted with the same time delay, the timing skew error between the clock signal and the data signal during transmission can be reduced. However, this scheme also has a shortcoming. That is, in order to detect a clock signal from a received signal, a source driver compares the level of the received signal with each level of a reference signal. If the level of a common component between a clock signal and a data signal received at the source driver changes, the embedded clock signal cannot be detected accurately.